Heterogeneous integration of high performance electrical, micro-electro-mechanical, and optoelectronic devices together onto the same substrate is very important for the development of low-cost and/or high-performance/density Microsystems.
Integrating different materials and different device functions is widely recognized because of its wide applications in the market. But there are inherent problems in combining different materials. Amongst those problems, are differences in thermal expansion coefficient between different materials. For example, the thermal expansion mismatch is very large between silicon, the primary material of interest for large-scale high-density integrated circuits, and III–V compounds, the materials of interest for optoelectronic and microwave devices and circuits.
The current microengineering tool kit is capable of producing a great range of sensor and actuator devices. This set of fabrication method consists mainly of bulk and surface silicon micromachining, laser micro-machining, and LIGA (German acronym for Lithographic Galvanoformung Abformung). In the next generation of MEMS, micromechanical sensors and actuators will be integrated with electronic and optical components to give powerful and complex Microsystems. The integration of microelectromechanical systems (MEMS) sensors and actuators with other classes of microcomponents-electronic, optical and electromechanical devices onto a single substrate has the potential to create powerful and complex Microsystems.
As the market for low cost and high performance electronic, optoelectronic, and electromechanical integrated circuits increases, many new assembly and integration techniques must be developed. It has become increasingly important to integrate high performance low cost electronic, optoelectronic and/or radio frequency components onto dissimilar substrates. To improve system performance and reduce assembly cost, often compound semiconductor devices must be integrated monolithically to active circuitry contained in the substrate. Primary interest among these is integrating these types of devices with silicon CMOS (Complementary Metal Oxide Semiconductor) technology, in order to increase the number of on-wafer functions available, and ultimately reduce the cost, size, and weight of micro-device based systems.
Current integration strategies often rely on “pick and place” serial assembly techniques, which encounter speed and cost constraints in applications that require the assembly of large numbers of microscale components with high positioning precision. In addition, surface forces must be carefully controlled to prevent unwanted adhesion of microscopic parts to each other or tool surfaces. Because of these disadvantages new low-cost parallel assembly techniques are being investigated and commercialized.
As the dimensions of micro-electronic, micro-optoelectronic and micro-electromechanical devices and systems decrease, and as their complexity increases, there is a need to use self assembly and integration techniques to simplify the processing of these devices.
Several approaches have been proposed for fabricating and assembling of different micro-devices (or generally microstructures) onto a substrate. Such proposed approaches include, selective area growth, flip-chip bonding, epitaxial lift-off (ELO), electrostatic alignment, and fluidic self-assembly. However, each of these approaches has drawbacks and technological issues, and the serious limitation of these approaches limit their utility in actual applications.
A selective area growth approach was investigated early as a potential method of heterogeneous integration. In this approach one grows GaAs or InP devices directly onto a silicon substrate. This approach becomes limiting due to lattice mismatch and thermal property mismatch between Si and GaAs. The devices grown on silicon are not as good devices as those grown on a lattice-matched substrate. In addition, growing GaAs onto silicon is inherently difficult and therefore very costly. Accordingly, InP or GaAs cannot efficiently be grown on a silicon substrate.
Another approach is the optical solder bump method for heterogeneous integration. The approach of the optical solder bump method is to put compound semiconductor heterostructures in recesses formed in the surface of integrated circuit wafers and then fabricate those heterostructures into devices monolithically integrated with the pre-existing VLSI (Very Large Scale Integration) electronic circuitry. The fully processed active devices are individually placed onto bonding sites with a mechanical pick-and-place tool. The devices are held into place by solder bonding, and then the substrate is removed by using etching, if desired. This approach also has serious limitations. Because this process involves serial manipulation and alignment of individual device, it is expensive and time consuming.
For the most part heterogeneous integration is currently achieved by using some variation of the solder bump process to attach modest size arrays of devices—e.g. in attaching vertical-cavity surface emitting lasers (VCSELs) on individual integrated circuit chips. However, this approach also has major drawbacks. The bonding temperature is very important for the size of the device arrays that can be bonded, and is typically limited to a centimeter on a side. Device array substrates must be thinned and totally removed to separate the device in the array from one another. This involves additional processing. The current industry standard for silicon integrated circuit wafers is 200 mm in diameter, and for GaAs wafers it is 150 mm, because of difference in diameter bonding full wafers is impractical. To overcome this problem, one is forced to bond pieces of wafers and to use a tiling process to cover a full wafer.
Other approaches for heterogeneous integration include epitaxial transfer procedures such as appliqué and ELO. For both processes, an epitaxial layer is generally released from its growth substrate, either by etching the substrate down to an etch-stop layer in appliqué technique or by etching a sacrificial layer in ELO technique. The layer, which is typically supported by a polymer membrane or wax, is then bonded to host substrate through van der Waals bonding or with a metal bond. The devices can be processed either before or after the transfer of the epitaxial layer to the host substrate depending upon the process requirements. However, both appliqué and ELO techniques have disadvantages. Such disadvantages include that handling extremely thin epitaxial layers is difficult and tedious, and any pre-processed devices need to be aligned to existing circuitry on the host substrate, which is time consuming and difficult when compounded with the thinness of the epitaxial film.
Another approach proposed, wafer bonding, is used to transfer an entire epitaxial layer. In this method, an epitaxial structure is grown upside down on a growth wafer. The host wafer and the growth wafer are bonded together, and the growth wafer is removed to expose the epitaxial layers. The epitaxial layer is then processed to create devices. This method also has major drawbacks, Due to thermal expansion mismatch of the wafers, and due to different thermal budgets for the two different materials, bonded wafers suffer from thermal limitations.
A yet further approach is to begin with individual devices and attach each in its proper position on the integrated circuit surface. At first such an approach sounds impractical, but upon much thought one realizes that it offers significant advantages once the assembly process is perfected. It circumvents the problem of smaller compound semiconductor wafer sizes, it can be used to assemble several different types of devices on a single substrate, and it can be used with any material with minimal concern with thermal expansion coefficient.
For successful, efficient heterogeneous integration, a method that will align separate discrete die without individual manipulation of the devices is required. There have been some approaches that meet these requirements. These approaches include vector potential parts manipulation, DNA and electrophoresis-assisted assembly, and fluidic self-assembly techniques. These techniques each involve the assembling and integration of many individual units on processed integrated circuits (or other electronic substrates). The individual units (or microstructures) may be a single devices, small assemblies of devices, or full integrated circuits.
The vector potential parts manipulation process allows for the alignment of separate device in an assembly. This process most often uses electrostatics, to direct and place units. Units are placed on a vibrating stage and are attracted to potential wells on the substrate. As the vibration is reduced, the units position into place. At present, this method has been used to manipulate relatively large parts using high voltages in a specially prepared alignment fixture.
In the DNA and electrophoresis-assisted assembly technique, a DNA-like polymer film is formed on the individual parts and a complementary film is patterned on the wafer or on the circuit surface where the parts are to be placed. The attraction force between the two complementary DNA films then locates and holds the parts in position. An electrophoresis approach is also used to attract and place device parts on a surface electrode pattern.
In the fluidic self-assembly approach, carefully etched devices are placed in a substrate with etched recesses of matching dimensions. It is one process that will align and place separate devices without individual manipulation. The host substrate is patterned with deep recesses that match the shape of the device. The specially shaped devices are separated from the growth substrate, suspended in a fluid, and flowed over the surface of the host substrate, and gravity is relied upon to get the devices into the recesses and to hold them there. However, fluidic self-assembly requires that the devices are trapezoidally shaped, to match the recesses in the substrate. This shape requirement is difficult to achieve and adds several processing steps, such as ion-milling.
Accordingly, it is one object of the present invention to provide a new technique of assembling and integration of microstructures onto a silicon wafers or on the separate substrate, which is of low cost, very compact, efficient, reliable, and requires minimum maintenance.
It is a further object of the invention to provide a technique of assembling and integration of microstructures onto a substrate that can be carried out in such a manner to avoid damaging the preexisting electronics on the substrate.
It is a yet further object of the invention to provide a new technique of assembling and integration of microstructures onto a substrate that takes full advantages of the very large diameter silicon wafers.